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Autograders
RTL-aware grading for Verilog assignments. Functional, structural, and timing checks with student-readable feedback.
Autograders, simulation infrastructure, and supplemental course materials, developed for the computer architecture curriculum at UW–Madison.
RTL-aware grading for Verilog assignments. Functional, structural, and timing checks with student-readable feedback.
In-browser logic and RISC-V simulators. No install, no toolchain — works on a Chromebook in lab.
Hundreds of self-contained problems with worked diagrams, covering everything from K-maps to pipelined datapaths.
One command to bring up a reproducible Verilog + synthesis + FPGA flow. Vivado, Quartus, and open-source backends.
Lightweight instructor dashboard for cohorts, assignment release, regrade flows, and gradebook export.
Every piece is MIT-licensed and lives on GitHub. Fork it, deploy it, contribute back upstream.
| Code | Title | Theme |
|---|---|---|
| ECE 252 | Introduction to Computer Engineering | Foundations |
| ECE 352 | Digital System Fundamentals | Digital Logic |
| ECE 551 | Digital System Design & Synthesis | Verilog & HDL |
| ECE 552 | Introduction to Computer Architecture | Architecture |
| ECE 554 | Digital Engineering Laboratory | Capstone |
Plus supplemental material — sub-modules of the above, for instructors who only want one piece.
Three days of setup, not three months. Everything is forkable, the autograder runs in your CI, and the simulators are static pages.
Read the instructor handbook and pick the modules that map to your syllabus.
Clone the monorepo. Rename, rebrand, drop the modules you don't need.
One command brings up the autograder + sims. Point your LMS at it.
Authoring institution
TODO
Open for adoption